The present disclosure generally relates to memory architecture, and more specifically, to an architecture of a semiconductor memory array.
Semiconductor memory cells may be organized in memory arrays, so that each memory cell is connected to a local bit line and to a word line. At least one local bit line may be evaluated with a local evaluation circuit connected to a global bit line (GBL). The GBL may be used within a relatively high capacity memory array. Drawing the GBL to ground can therefore require a relatively large field-effect transistor (FET). Large FET devices can experience significant leakage currents, which can cause increased chip power consumption relative to smaller FET devices.